The invention relates to a method and to a device for stabilizing a transfer function of a digital phase locked loop.
FIG. 1 shows a schematic block diagram of a digital phase locked loop PLL internally known to the applicant. The digital phase locked loop PLL has a phase detector BPD, a loop filter LF, a digitally controlled oscillator device DCO and a divider device TV.
The binary phase detector (BPD) determines a digital binary phase difference signal ε between a feedback clock signal fc and a reference clock signal rc. The binary phase detector provides the digital phase difference signal ε at the input of the loop filter LF. The loop filter LF generates in dependence on the digital phase difference signal ε provided an oscillator control signal ω by means of which the digitally controlled oscillator device (DCO) can be controlled. To generate the oscillator control signal ω, the loop filter LF has a first loop filter path LFP1 and a second loop filter path LFP2. The first loop filter path LFP1 is constructed as a proportional path for amplifying the digital phase difference signal ε provided. To provide higher gains, the second loop filter path LFP2 is constructed as an integral path.
The first loop filter path LFP1 has a first amplifying unit VE1 and a first timing element ZG1. The first amplifying unit VE1 receives at its input the digital phase difference signal ε and amplifies it by the gain factor β. The phase difference signal ε amplified by the gain factor β is supplied to the first timing element ZG1 which models latency times based on the hardware and delays the amplified phase difference signal ε.
The second loop filter path LFP2 has an integrator unit IE, a second amplifying unit VE2 and a second timing element ZG2. The integrator unit IE has a first addition device AV1 which adds the digital phase difference signal ε and an integrated phase difference signal ψ fed back via a third timing element ZG3. The integrated phase difference signal ψ is amplified by a gain factor α of the second loop filter path LFP2 by means of the second amplifying unit VE2. The second timing element ZG2, like the first timing element ZG1, models latency times based on the hardware and delays the integrated phase difference signal ψ.
In addition, the digital phase locked loop PLL has a second addition device AV2 which adds the output signals of the first loop filter path LFP1 and of the second loop filter path LFP2 for forming the oscillator control signal ω.
The oscillator device DCO can be controlled by means of the oscillator control signal ω and outputs a digital output clock signal dco in dependence on the oscillator control signal ω received.
The digital phase locked loop PLL also has a feedback branch between the oscillator device DCO and the phase detector BPD. In the feedback branch, a divider device TV is provided which divides the output clock signal dco of the oscillator device DCO by means of a divider factor N and provides the feedback clock signal fc at the output end. The feedback clock signal fc has an N-fold frequency of the output clock signal dco, where N is the divider factor of the divider device TV. The feedback clock signal fc is also used for clocking the loop filter LF.
FIG. 2 shows a diagrammatic representation of a linear model of the digital phase locked loop PLL according to FIG. 1. The phase detector BPD is identified by a linearized gain Kbpd and the oscillator device (DCO) is characterized by the constant gain KT. From “Jitter Transfer Analysis of Tracked Oversampling Techniques for Multigigabit Clock and Data Recovery,” IEEE Trans. on Circ. Syst. Part II, vol. 50, November 2003, Y. Choi, D. K. Joeng and W. Kim, it is known that the value of the gain Kbpd of the phase detector BPD is dependent on the fluctuation or jitter σtr of the reference clock signal rc. This results in the following relationship between the gain Kbpd and the jitter σtr:Kbpd=2/(√{square root over (2π)}σtr)  (1)
Due to the dependence of the transfer function of the phase locked loop PLL according to FIG. 2 on the gain Kbpd of the phase detector BPD, the transfer function itself is also dependent on the jitter σtr. The system characteristics such as bandwidth or signal/noise ratio of the phase locked loop thus change in dependence on the reference clock signal rc.
Since the statistical characteristics of the reference clock signal rc are unknown a priori, the disturbances caused by the jitter σtr can also not be eliminated a priori.
Some methods and circuits have hitherto become known which attempt to solve the problem of the jitter of the reference clock signal. For example, in “Jitter Transfer Analysis of Tracked Oversampling Techniques for Multigigabit Clock and Data Recovery,” IEEE Trans. on Circ. Syst. Part II, vol. 50, November 2003, Y. Choi, D. K. Jeong and W. Kim, a circuit is described in which the number of quantization stages in the phase detector BPD is increased. This method can be used when the jitter is sufficiently large. However, if the jitter values are small, this method is reduced to a conventional one-bit phase detector so that the problem as such can no longer be solved at all. However, the setting-up of a number of quantization stages also means a much higher and thus more expensive hardware complexity. In addition, more energy and more chip area is needed by using the multiplicity of quantization stages.
From “A 2.5-10 Gb/s CMOS transceiver with alternating edge sampling phase detector for loop characteristic stabilization,” in ISSCC Dig. Tech. Papers, 2003, B. J. Lee, M. S. Hwang, S. Lee and D. K. Jeong, and “A 5 Gb/s/s 0.25 μm CMOS jitter tolerant variable interval oversampling clock/data recovery circuits,” in ISSCC Dig. Tech. Papers 2002, S. Lee, M. S. Hwang, Y. Choi, S. Kim, Y. Moon, B. J. Lee, D. K. Jeong, K. Kim, Y. J. Park and G. Ahn, analogous methods or circuits have been known which adjust the gain Kbpd of the phase detector BPD for meeting bandwidth and signal/noise ratio requirements of the phase locked loop.
A disadvantage of these methods or circuits which have become known is generally that they require an increased outlay of analog circuits. An increased outlay of analog circuits means a higher consumption of chip area and energy and is thus cost-intensive. In addition, these known methods and circuits only have the aim of adjusting the gain Kbpd of the phase detector. This leaves out of consideration an adaptation of gain KT of the oscillator device which can change over time due to disturbances.